(1) Field of the Invention
The present invention relates to a solid-state imaging apparatus which is suitable for an image input apparatus such as a video camera and a digital still camera, and in particular, to a sampling circuit which reads out a signal from a Metal Oxide Semiconductor (MOS) imaging apparatus or Complementary Metal Oxide Semiconductor (CMOS) imaging apparatus.
(2) Description of the Related Art
Due to the widespread use of image input devices such as video cameras and digital still cameras, various types of solid-state imaging apparatuses have been suggested (for example, refer to Japanese Laid-Open Patent application No. H-10-173997).
FIG. 1 is a circuit diagram of a conventional solid-state imaging apparatus. A unit pixel (photodiode) includes: a photodiode PD; a read-out MOS transistor M1; a floating diffusion FD; a reset MOS switch M2; an amplified MOS switch M3; and a row-selecting MOS switch M4. A vertical shift register 90 controls the operation in the pixel per row. A Correlated Double Sampling circuit (hereinafter referred to as CDS circuit) which includes a sampling MOS switch M12, a clamp capacitor capacity CCL, a sampling capacitor capacity CSH and a clamp MOS switch M16 is connected to each of column signal lines VSIGn and VSIGn+1. A signal whose fixed pattern noise of the pixel has been suppressed in the CDS circuit is outputted to a horizontal signal line HSIG, via a column-selecting MOS switch M14 controlled by a horizontal shift register 91, so as to be outputted as an image signal, via an amplifier AMP92 and a CDS93. Here, a VHB application circuit for applying a bias voltage VHB synchronized with a horizontal signal line reset pulse φ HR to the horizontal signal line HSIG is connected to the horizontal signal line HSIG, the circuit including a horizontal signal line reset MOS switch M15 and a constant voltage source VHB.
FIG. 2 is a timing chart showing operations of the conventional solid-state imaging apparatus as shown in FIG. 1. The concrete operation of the unit pixel is as follows. As shown in FIG. 2, during certain horizontal blanking period HBLK, in the pixel row of the corresponding horizontal scanning line (for example, mth row), first, the floating diffusion FD is reset to a supply voltage VDD, using a row-resetting pulse φ VRSTm outputted from the vertical shift register 90. Immediately, a row-selecting pulse φ VSLm is raised so that the reset level of the pixel is outputted to the column signal line VSIGn, floating diffusion FD of the pixel being in the reset state.
Using the above mentioned reset level of the pixel, the CDS circuit connected to the column signal line VSIGn executes the first sampling operation (hereinafter referred to as clamp). In the clamp, while (i) via the sampling MOS switch M12, the reset level of the pixel (the first pixel signal) is provided to the first electrode of the clamp capacitor CCL (the electrode connected to the sampling MOS switch M12), and (ii) via the clamp MOS switch M16, a clamp voltage VCL is applied to the second electrode of the clamp capacitor CCL (the electrode connected to the clamp MOS switch M16), a clamp pulse φ CL applied to a control electrode (hereinafter referred to as a gate electrode) of the clamp MOS switch M16 is reduced, so as to hold the clamp voltage VCL at the node between the clamp capacitor CCL and the sampling capacitor CSH (from t=t1 to t=t2).
Then, a row read-out pulse φ VRDm is raised in the middle of the same horizontal blanking period HBLK, and a signal charge is transferred from the photodiode PD to the floating diffusion FD. Since the change associated with the signal charge appears as a signal level (the second pixel signal) in the column signal line VSIGn, the CDS circuit executes the second sampling operation (hereinafter referred to as sampling), using the above mentioned signal level. In the sampling, (i) a sample pulse φ SH is changed to low level, and (ii) the voltage change (difference between the signal level and the reset level) in the column signal line VSIGn is held at the node between the clamp capacitor CCL and the sampling capacitor CSH (from t=t3 to t=t4). Here, the voltage held at the node has the value which has changed, from the clamp voltage VCL, by the dividing ratio of the capacity of the clamp capacitor CCL to the sampling capacitor CSH that is the difference between the signal level and the reset level. Thus, unevenness of the threshold voltages of the amplified MOS switch M3 in the unit pixel is deducted, and the fixed pattern noise of the pixel is suppressed.
The held voltage as described above sequentially appears per column in the horizontal signal line HSIG, via the column-selecting MOS switch M14 controlled by the horizontal shift register 91 (from t=t5 to t=t6). Here, due to the capacity division between the sampling capacitor CSH and the capacity CH of the horizontal signal line HISG, the voltage of the horizontal signal line HSIG changes, and the changed voltage is outputted as a pixel signal.
However, according to the conventional sampling circuit as described above, there is a problem that fixed pattern noise is generated, due to unevenness of the threshold voltages (unevenness among each column signal) of the MOS switch included in the CDS circuit connected to each column signal line.
The predominant mechanism in which unevenness occurs in respective sampling voltage in each of a plurality of sampling circuits, is as follows.
As shown in FIG. 3A, the sampling circuit basically includes a MOS switch and a capacitor CSH, and operates by changing a gate voltage φ SH so that the MOS switch becomes OFF state from ON state. Such equivalent circuit becomes (i) a circuit as shown in FIG. 3B when the MOS switch has ON state, and (ii) a circuit as shown in FIG. 3C when the MOS switch has OFF state. As shown in the equivalent circuit in FIG. 3B, in the ON state, an input signal VIN and the sampling capacitor capacity CSH are in conduction state in which a sampling pulse φ SH is capacitively coupled with a gate capacitor CG of the MOS switch. Here, the gate capacitor CG has a total sum of (i) a gate-source capacity CGS, (ii) a gate-drain capacity CGD and (iii) a gate oxide film capacity CGO (between channels) when the MOS switch is in the operation point of the linear area. On the other hand, as shown in the equivalent circuit of FIG. 3C, as the capacitor model changes in the OFF state, (i) the input signal VIN is capacitively coupled to the sampling pulse φ SH via the gate-drain capacity CGD, (ii) the sampling capacitor capacity CSH is capacitively connected to the sampling pulse φSH via the gate-source capacity CGS, and (iii) the input signal VIN and the sampling capacitor capacity CSH are in non-conduction state.
Using the capacitor model of the MOS switch as described above, as shown in FIG. 4A, in the case where two same sampling circuits are structured by a MOS switch which has different threshold voltages Vth1 and Vth2, due to the difference (unevenness) ΔVth of the threshold voltages as shown in FIG. 4B, the difference (unevenness) ΔSH of the sampled voltages occurs, as shown in the following equations.
                              VSH1          =                      VIN            -                                                            C                  GS                                                  (                                                            C                      SH                                        +                                          C                      GS                                                        )                                            ⁢                              V                th1                                                    ⁢                                  ⁢                  VSH2          =                      VIN            -                                                            C                  GS                                                  (                                                            C                      SH                                        +                                          C                      GS                                                        )                                            ⁢                              V                th2                                                    ⁢                                  ⁢                              Δ            ⁢                                                  ⁢            VSH                    =                                    VSH1              -              VSH2                        =                                                            C                  GS                                                  (                                                            C                      SH                                        +                                          C                      GS                                                        )                                            ⁢              Δ              ⁢                                                          ⁢                              V                th                                                                        [                  Equation          ⁢                                          ⁢          1                ]            
According to the above mentioned mechanism, in the conventional solid-state imaging apparatus as shown in FIG. 1, unevenness occurs in the following operation phase.
(Clamp phase; from t=t1 to t=t2 in FIG. 2)
FIG. 5A is a circuit diagram showing only the part related to the clamp phase in the conventional circuit, in relation to the above mentioned phase, that is, the operation in which the first pixel signal is sampled. Here, the threshold value unevenness of the clamp MOS switch M16 in which a clamp pulse φ CL is applied is Δ Vth-clamp. The gate-source capacity of the clamp MOS switch M16 is CGS. The sampling capacitor capacity is CSH, and the clamp capacitor capacity CCL. The unevenness of the electric charge Δ QCSH-clamp (conversion of the threshold unevenness into electric charge) accumulated into the sampling capacitor can be shown in the following equation.
                              Δ          ⁢                                          ⁢                      Q                                          C                SH                            -              clamp                                      =                              -                                                            C                  SH                                ⁢                                  C                  GS                                                                              C                  SH                                +                                  C                  CL                                +                                  C                  GS                                                              ⁢          Δ          ⁢                                          ⁢                      V                          th              -              clamp                                                          [                  Equation          ⁢                                          ⁢          2                ]            (Sample phase; from t=t3 to t=t4 in FIG. 2)
FIG. 5B is a circuit diagram showing only the part related to the sample phase in the conventional circuit, in relation to the above mentioned phase, that is, the operation in which the second pixel signal is sampled. Here, the threshold unevenness of the sampling MOS switch M12 in which the sample pulse φ SH is applied is Δ Vth-sample. The gate-source capacity of the MOS switch is CGS. The sampling capacitor capacity is CSH, and the clamp capacitor capacity is CCL. The unevenness of the electric charge Δ QCSH-sample accumulated into the sampling capacitor capacity can be shown in the following equation.
                              Δ          ⁢                                          ⁢                      Q                                          C                SH                            -              sample                                      =                              -                                                                                                      C                      SH                                        ⁢                                          C                      CL                                                                                                  C                      SH                                        +                                          C                      CL                                                                      ⁢                                  C                  GS                                                                                                                        C                      SH                                        ⁢                                          C                      CL                                                                                                  C                      SH                                        +                                          C                      CL                                                                      +                                  C                  GS                                                              ⁢          Δ          ⁢                                          ⁢                      V                          th              -              sample                                                          [                  Equation          ⁢                                          ⁢          3                ]            (Horizontal output phase; from t=t5 to t=t6 in FIG. 2)
FIG. 5C is a circuit diagram showing only the part related to the horizontal output phase in the conventional circuit, in relation to the above mentioned phase, that is, the operation in which the signal voltage stored in the sampling capacitor is outputted to the horizontal signal line. Here, the threshold value unevenness of the column-selecting MOS switch M14 in which the column-selecting pulse φ Hn is applied is Δ Vth-HSW. The gate-source capacity of the MOS switch is CGS. The gate-drain capacity is CGD. And, the total sum of the CGS, CGD and the capacity of the gate oxide film is CG. The unevenness of the electric charge quantity Δ QCSHCH-Hout which appears in the horizontal signal line that has the sampling capacitor and the horizontal signal line capacity CH can be shown in the following equation.
                              Δ          ⁢                                          ⁢                      Q                                                            C                  SH                                ⁢                                  C                  H                                            -              Hout                                      =                              (                                                                                C                    SH                                    ⁢                                      C                    GS                                                                                        C                    SH                                    +                                      C                    GS                                                              +                                                                    C                    H                                    ⁢                                      C                    GD                                                                                        C                    H                                    +                                      C                    GD                                                              -                                                                    (                                                                  C                        SH                                            +                                              C                        H                                                              )                                    ⁢                                      C                    G                                                                                        C                    SH                                    +                                      C                    H                                    +                                      C                    G                                                                        )                    ⁢          Δ          ⁢                                          ⁢                      V                          th              -              HSW                                                          [                  Equation          ⁢                                          ⁢          4                ]            
In the above mentioned three phases, due to the threshold value unevenness of the individually independent MOS switch, the electric charge unevenness occurs. Thus, the unevenness occurring in all of the phases is added, and becomes a longitudinal fixed pattern noise. If such longitudinal fixed pattern noise is converted into unevenness of signal voltages appearing in the horizontal signal line, the value can be shown in the following equation.
                              Δ          ⁢                                          ⁢          V                =                              1                                          C                SH                            +                              C                H                                              ⁢                      (                                          Δ                ⁢                                                                  ⁢                                  Q                                                            C                      SH                                        -                    clamp                                                              +                              Δ                ⁢                                                                  ⁢                                  Q                                                            C                      SH                                        -                    sample                                                              +                              Δ                ⁢                                                                  ⁢                                  Q                                                                                    C                        SH                                            ⁢                                              C                        H                                                              -                    Hout                                                                        )                                              [                  Equation          ⁢                                          ⁢          5                ]            
In other words, due to the unevenness of the threshold voltages (non-uniformity among each CDS circuit) among (i) the clamp MOS switch M16 structuring the CDS circuit connected to each column signal, (ii) the sampling MOS switch M12 and (iii) the column-selecting MOS switch M14, even with the same input signal, a different voltage is generated for each column. As a result, according to the conventional circuit structure, unless the threshold value unevenness of the MOS switch is removed, the longitudinal fixed pattern noise cannot be controlled.